1. Technical Field
The present invention relates generally to semiconductor device fabrication, and more particularly, to methods of manufacturing a semiconductor structure including a deep trench isolation in which the channel stop is formed prior to deep trench etch.
2. Related Art
In semiconductor devices, a number of transistors are generated in very close proximity to one another and isolated from one another by insulating deep trenches. For example, NPN transistor devices are typically formed with a collector that runs laterally through a sub-collector and then up to a contact level. The collectors terminate in an n-type substrate about 2 um deep. In order to isolate the different NPN devices on the wafer, a deep trench isolation in the form of an annulus is formed about the device down into the substrate to isolate the sub-collector of each NPN device from adjacent sub-collectors of other devices.
In order for a deep trench to fully isolate a device, it must include a channel stop at a lower end thereof within the substrate. In particular, if a deep trench is formed in, for example, an N+ subcollector, it extends into a P− substrate thereunder. In this situation, a deep trench isolation may invert, i.e., attract electrons, such that current can leak around the bottom of the deep trench isolation, resulting in current flowing between adjacent sub-collectors. To prevent inversion, deep trench isolations are typically formed with a channel stop that includes a dopant type that matches the substrate to prevent the deep trench isolation from inverting. In the above example, the dopant type would be p-type (e.g., boron) to match the substrate.
One issue relative to formation of deep trench isolations is when to form them during the fabrication process. Conventionally, deep trench isolations are formed in a substrate and then covered during transistor device fabrication. For example, in conventional processing, the following steps are completed prior to device fabrication: etching of a deep trench, forming a channel stop in the bottom of the deep trench, and finally filling of the deep trench with a dielectric. Formation of a channel stop is completed after the deep trench is etched, for example, by using a p-type (e.g., boron) implant into the bottom of the deep trench. This process is advantageous because as processing proceeds through front-end-of-line (FEOL) fabrication, i.e., device formation and metallization, the implant is exposed to a number of thermal cycles that activate the channel stop. The annealing allows the sharing of collector level between the devices (e.g., SiGE NPNs) because the collectors of adjacent devices are isolated from each other by the deep trench isolation. Without the channel stop, the bottom of the deep trench isolation is inverted and the collectors are electrically tied together.
In more advanced processing, however, it has been found advantageous from a cost perspective to generate deep trench isolations at the end of FEOL fabrication, i.e., after device formation and metallization. This latter situation, however, does not provide the thermal cycles required to activate the dopant of the channel stop for the deep trench isolations. Accordingly, a conventional channel stop cannot be used with the low cost deep trench isolation processing. As a result, shared deep trench isolations cannot be used because of inversion shorts. If a conventional channel stop is to be used, it would require device-to-device spacing that is vastly enlarged because a P-well must be inserted between the deep trench isolations of each device to create the isolation. This situation is untenable. In addition, for improved transistor packing density, it remains advantageous to have one large subcollector shape with multiple devices inside a big shape. This structure is only effective if shared deep trench isolations can be used.
In view of the foregoing, there is a need in the art for a way to form a deep trench isolation at the end of FEOL processing.